The present invention relates to a semiconductor stack for performing a logic operation that has a capability of storing information related to/involved in the logic operation.
For performing logic operations, it is known to use multiple, individual electronic devices such as, for example, electronic transistors, which are connected to each other, in an electrical circuit. To perform a given logic operation, a given set of electronic devices in a predefined electrical circuit is used. So that different logic operations may be performed, each electrical circuit predefined and/or allocated for the performance of a given logic operation, via its constituent given set of electronic devices, may be embedded in an integrated circuit and/or a semiconductor device.
A problem associated with performing logic operations using an integrated circuit and/or semiconductor device as above-described may be limited flexibility and/or versatility since a given logic operation may only be performed by an electrical circuit comprising a given set of electronic devices predefined for the performance of that task and not interchangeably with and/or between other electrical circuits configured, or having the ability to perform logic operations. A further related problem may be that, since a specific amount of space is to be reserved for the integration of the electrical circuits, each predefined to perform a given logic operation, the density of an integrated circuit/device using such electrical circuits to perform logic operations may be relatively reduced.
In known logic devices and/or applications, logic functionality is based on information that is volatile, such as, for example, charge. In this regard, the information representing the logic inputs is obtained from storage, a given logic operation is performed on the logic inputs and the result of the logic operation, the logic output, is stored away. To be provided in respect of the information involved in/related to the logic operation, namely the logic inputs and the logic output, are resources to conduct the steps for obtaining the logic inputs and storing the logic output and space/memory for storing such information.
U.S. Pat. No. 7,186,998B2 discloses a multi-terminal logic device, which includes a phase-change material having crystalline and amorphous states in electrical communication with three or more electrical terminals. The phase-change material is able to undergo reversible transformations between amorphous and crystalline states in response to applied electrical energy where the amorphous and crystalline states show measurably distinct electrical resistances. Electrical energy in the form of current or voltage pulses applied between a pair of terminals influences the structural state and measured electrical resistance between the terminals. In the devices disclosed in this document, independent input signals are provided between different pairs of terminals and the output is measured as the resistance between yet another pair of terminals. Logic functionality is achieved through relationships between the applied input signals and the measured output resistance where the relationship is governed by the effect of the input signals on the structural state and the electrical resistance of the phase-change material. Logic values may be associated with the crystalline and amorphous states of the phase-change material or the measured resistance between a pair of terminals. U.S. Pat. No. 7,186,998B2 discloses a method of operating a phase-change memory cell, thereby to achieve a given logic functionality. The disclosed phase-change memory cell has three terminals, whereby the respective input signals applied across two different pairs of terminals may be used to create crystalline or amorphous states in the phase-change material, having corresponding resistances that are discernible from each other and that may be used to represent requisite inputs of a given logic function. An output resistance measured between a third pair of terminals corresponds to the output of the logic function.
US2011/0096594A1 discloses techniques for reading phase change memory that mitigate resistance drift. One contemplated method includes applying a plurality of electrical input signals to the memory cell. The method includes measuring a plurality of electrical output signals from the memory cell resulting from the plurality of electrical input signals. The method includes calculating an invariant component of the plurality of electrical output signals dependent on the configuration of amorphous material in the memory cell. The method also includes determining a memory state of the memory cell based on the invariant component. In one embodiment of the invention disclosed in that document, the method further includes mapping the plurality of electrical output signals to a measurements region of a plurality of measurements regions. The measurements regions correspond to memory states of the memory cell.